1. Field of the Invention
Example embodiments of the present invention relate generally to a phase-locked loop and method thereof and a phase-frequency detector and method thereof, and more particularly to a phase-locked loop and a phase-frequency detector with reduced performance errors and methods thereof.
2. Description of the Related Art
A phase-locked loop (PLL) and/or a delay-locked loop (DLL) may be employed in conventional digital communication systems to transmit data at higher speeds while maintaining a reliable data transfer. In the phase-locked loop, a phase-frequency detector may compare a phase of a reference signal with a phase of a signal received from a voltage-controlled oscillator (VCO). An output Of the phase-frequency detector may be applied to a charge pump to generate a phase detection signal varying in accordance with the phase difference between the reference signal and the VCO signal. A loop filter may perform a low pass filtering operation on the detected phase detection signal to generate a control voltage signal, which may be output to the VCO. The VCO may generate the VCO signal based on the control voltage signal received from the loop filter. The VCO signal may be divided by a loop divider and output to the phase-frequency detector to be compared with the reference signal.
FIG. 1 is a circuit diagram illustrating a conventional phase-frequency detector. Referring to FIG. 1, the conventional phase-frequency detector may include a first flip-flop 10, a second flip-flop 12 and an AND gate 14. The first flip-flop 10 may generate an up signal UP based upon a detection of a rising edge of the reference signal REF. The second flip-flop 12 may generate a down signal DN based upon a detection of a rising edge of a comparison signal FDB. The AND gate 14 may perform an AND operation of the up signal UP and the down signal DN to generate respective reset signals for the first and second flip-flops 10 and 12. The up signal UP may control an up current source of a charge pump 20 and the down signal DN may control a down current source of the charge pump 20.
A phenomenon referred to as a “dead zone” may occur during an operation of the conventional phase-frequency detector. If a phase difference between two input signals is low, the up signal UP may not reach a first logic level (e.g., a higher logic level or logic “1”) due to the time required to charge a load capacitor of a switch (e.g., one or more of switches S1 and S2 which may be implemented as field effect transistors (FETs)) of the charge pump 20 (e.g., the up signal UP may not exceed a threshold voltage of the switch). Thus, the up signal UP and the down signal DN may instead be set to a second logic level (e.g., a low logic level or logic “0”). The dead zone may occur where the phase-frequency detector may not produce the up signal UP and the down signal DN for charging and discharging the charge pump despite the presence of a phase difference between the two input signals.
Occurrences of dead zones may be reduced by decreasing a rising time (e.g., a time period required to transition to the first logic level) of the up signal UP and the down signal DN output from the phase-frequency detector. As discussed above, the switches S1 and S2 of the charge pump 20 may be implemented as FETs, and reduction in capacitor loads associated with FETs may be difficult to achieve.
FIG. 2 is a graph illustrating a detected current based on a phase difference between two input signals received by the conventional phase-frequency detector in FIG. 1.
FIG. 3 is a circuit diagram illustrating another conventional phase-frequency detector. Referring to FIG. 3, another conventional phase-frequency detector may be configured similarly to the above-described phase-frequency of FIG. 1. However, this phase-frequency detector may further include a delay unit 16 for delaying a reset signal by the AND gate 14 for resetting the first and second flip-flops 10 and 12. Two input signals REF and FDB (e.g., a reference signal and a feedback signal, respectively) may be reset to the second logic level (e.g., a low logic level or logic “0”) such that the up signal UP and the down signal DN may be maintained at the first logic level (e.g., a high logic level or logic “1”) for a time period sufficient to reduce the dead zone.
FIG. 4 is a graph illustrating a detected current based on a phase difference between two input signals received by the conventional phase-frequency detector in FIG. 3.
Referring to FIG. 4, if both the up signal UP and the down signal DN are set to the first logic level (e.g., a high logic level or logic “1”), the switches S1 and S2 may each be turned on such that an “operating point” of the phase-frequency detector may move towards a centered position (e.g., see the directions indicated by the arrows illustrated in the graph of FIG. 4), which may thereby cause a glitch in the phase detection. If the delay added to the reset signal is increased (e.g., by the delay unit 16), a turn-on time of the switches S1 and S2 may likewise increase, which may thereby increase a frequency and/or duration of glitches.
Conventional phase-frequency detectors may be adapted to reduce pulse widths of the up signal UP and the down signal DN by controlling an output of the up signal UP and the down signal DN in response to the reset signal. However, if two input signals have substantially the same phases (e.g., where the phase difference may be close to zero), lower (e.g., minimum) pulse widths of the up signal UP and the down signal DN may be determined. Therefore, the dead zone may occur where the delay characteristics of the output gate are lower because the pulse widths of the up signal UP and the down signal DN may be set irrespective of the capacitance of the charge pump (e.g., charge pump 20). Further, as discussed above, adding delay (e.g., with the delay unit 16) to the output gate may reduce the dead zones at the expense of generating glitches or errors in the phase detection of the phase-frequency detector.